The present disclosure relates generally to memory devices and, more particularly, to jitter found on transmitted clocking signals of the memory devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Generally, a computing system may include an electronic device that, in operation, communicates information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM) device implemented on a dual in-line memory module (DIMM). In this manner, the processor may communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed by the processor, and/or store data output from the processor.
Over time, these electrical signals may degrade in quality due to, for example, aging of components of the electronic device. Degradation of electrical signals may increase a likelihood of clock jitter afflicting a system, where clock jitter relates to a clocking signal deviating from a desired clocking pattern such that a rising edge of a clocking signal occurs earlier than or later than a desired rising edge time in an unpredictable pattern such that compensating for the jitter is challenging. To facilitate improving operational reliability, performance of a memory device in response to extreme levels of clock jitter may be verified prior to finalization of manufacturing, for example, by an external verification device. In some instances, an external verification device may perform diagnostics on operation of the memory device after a memory device has completed manufacturing, for example, in the event that a customer returns a memory device to a manufacturer or prior to a manufacturer shipping the memory device for sale. In some instances, operation of a memory device may be verified based on analysis of signals indicative of data input to and/or output from the memory device, but not on the basis of how the memory device is responding internally between sub-components of the memory device to the clock jitter. In other words, accuracy of operational monitoring may be affected by performing verification activities by using an external verification device to the memory device and/or computing device. Furthermore, accuracy of operational monitoring may be affected by an external verification device being limited to the stages in a manufacturing process at which verification activities may be performed by the external verification device.